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Authors
Affiliations
1 Department of ECE, A.M.S. Engineering College, T.N., IN
2 ECE Department, A.M.S Engineering College, T.N., IN
3 A.M.S Engineering College, T.N., IN
4 VLSI Design, Department of ECE, A.M.S Engineering College, T.N., IN
Source
Programmable Device Circuits and Systems, Vol 4, No 5 (2012), Pagination: 255-259
Abstract
A probabilistic estimation bias (PEB) circuit for a fixed-width two’s complement Booth multiplier is proposed for Low Power and High accuracy. The proposed PEB circuit is derived from theoretical computation, instead of exhaustive simulations and heuristic compensation strategies that tend to introduce curve-fitting errors (interpolation) and exponential-grown simulation time. Consequently, the proposed PEB circuit provides a smaller area and a lower truncation error compared with existing works such as posttruncation and pre-truncation methodologies in Booth Multiplication. Implemented in an 8×8 2-D discrete cosine transform (DCT) core, the DCT core using the proposed PEB Booth multiplier improves the peak signal-to-noise ratio by 17 dB with only a 2% area penalty compared with the direct-truncated method. This PEB circuit also provides extensive applications in digital designs. PEB circuit are more easier to design and can achieve good simulation time in doing computations in higher order bits.
Keywords
Discrete Cosine Transform (DCT), Estimation Theory, Fixed-Width Booth Multiplier, Probabilistic Analysis.
